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Features
* Protocol
- UART Used as a Physical Layer - Based on the Intel Hex-type Records - Autobaud * In-System Programming - Read/Write Flash Memory - Read Device IDs - Block Erase - Full-chip Erase - Read/Write Configuration Bytes - Security Setting From ISP Command - Remote Application Start Command * In-Application Programming/Self-Programming - Read/Write Flash Memory - Read Device IDs - Block Erase - Read/Write Configuration Bytes - Bootloader Start
MP3 Microcontrollers
Description
This document describes the UART bootloader functionalities as well as the serial protocol to efficiently perform operations on the on-chip Flash memory. Additional information for the AT89C51SND1 product can be found in the AT89C51SND1 data sheet and the AT89C51SND1 errata sheet available on the Atmel web site, www.atmel.com. The bootloader software package (source code and binary) currently used for production is available from the Atmel web site.
AT89C51SND1 UART Bootloader
Bootloader Revision Revision 1.0.0 Revision 1.1.0
Purpose of Modifications New release increasing programming speed Bug fix in boot process
Date June 2002 October 2002
4241B-MP3-07/04
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Functional Description
In-System Programming Capability
The AT89C51SND1 bootloader facilitates In-System Programming and In-Application Programming. In-System Programming (ISP) allows the user to program or reprogram a microcontroller's on-chip Flash memory without removing it from the system and without the need of a pre-programmed application. The UART bootloader can manage a communication with a host through the serial network. It can also access and perform requested operations on the on-chip Flash memory.
In-Application Programming or SelfProgramming Capability
In-Application Programming (IAP) allows the reprogramming of a microcontroller's onchip Flash memory without removing it from the system and while the embedded application is running. The UART bootloader contains some Application Programming Interface routines named API routines allowing IAP by using the user's firmware.
Block Diagram
This section describes the different parts of the bootloader. Figure 1 shows the on-chip bootloader and IAP processes. Figure 1. Bootloader Process Description
External Host via the UART Protocol Communication On-chip User Application
ISP Communication Management
IAP User Call Management
Flash memory Management
Flash Memory
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ISP Communication Management The purpose of this process is to manage the communication and its protocol between the on-chip bootloader and an external device (host). The on-chip bootloader implements a serial protocol (see Section "Protocol", page 9). This process translates serial communication frames (UART) into Flash memory accesses (read, write, erase, etc.). Several Application Program Interface (API) calls are available to the application program to selectively erase and program Flash pages. All calls are made through a common interface (API calls) included in the bootloader. The purpose of this process is to translate the application request into internal Flash memory operations. This process manages low level accesses to the Flash memory (performs read and write accesses).
User Call Management
Flash Memory Management
Bootloader Configuration
Configuration and Manufacturer Information The table below lists configuration and manufacturer byte information used by the bootloader. This information can be accessed through a set of API or ISP commands. Table 1. Configuration and Munfacturer Byte Information
Mnemonic BSB SBV SSB Manufacturer ID1: Family code ID2: Product Name ID3: Product Revision Description Boot Status Byte Software Boot Vector Software Security Byte Default Value FFh F0h FCh 58h D7h ECh FFh
Mapping and Default Value of Hardware Security Byte
The 4 Most Significant Bytes (MSB) of the Hardware Byte can be read/written by software (this area is called Fuse bits). The 4 Least Significant Bytes (LSB) can only be read by software and written by hardware in parallel mode (with parallel programmer devices). Table 2. Mapping and Default Value of HSB
Bit Position 7 6 5 4 3 2 1 0 Mnemonic X2B BLJB Reserved Reserved Reserved LB2 LB1 LB0 Default Value U P U U U P U U To lock the chip (see datasheet) Description To start in x1 mode To map the boot area in code area between F000hFFFFh
Note:
U: Unprogrammed = 1, P: Program = 0
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Software Security Byte
The bootloader has Software Security Byte (SSB) to protect itself from user access or ISP access. The Software Security Byte (SSB) protects from ISP accesses. The command "Program Software Security Bit" can only write a higher priority level. There are three levels of security: * * level 0: NO_SECURITY (FFh) From level 0, one can write level 1 or level 2. level 1: WRITE_SECURITY (FEh) In this level it is impossible to write in the Flash memory, BSB and SBV. The bootloader returns an error message. From level 1, one can write only level 2. level 2: RD_WR_SECURITY (FCh) This is the default level. Level 2 forbids all read and write accesses to/from the Flash memory. The bootloader returns an error message.
*
Only a full-chip erase command can reset the software security bits. Table 3. Software Security Byte Levels
Level 0 Flash Fuse bit BSB & SBV SSB Manufacturer info Bootloader info Erase block Full chip erase Blank Check Any access allowed Any access allowed Any access allowed Any access allowed Read only access allowed Read only access allowed Allowed Allowed Allowed Level 1 Read only access allowed Read only access allowed Read only access allowed Write level2 allowed Read only access allowed Read only access allowed Not allowed Allowed Allowed Level 2 All access not allowed All access not allowed All access not allowed Read only access allowed Read only access allowed Read only access allowed Not allowed Allowed Allowed
Software Boot Vector
The Software Boot Vector (SBV) forces the execution of a user bootloader starting at address [SBV]00h in the application area (FM0). The way to start this user bootloader is described in the Section "Regular Boot Process", page 7.
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Figure 2. Software Boot Vector
UART Bootloader
User Bootloader Application [SBV]00h
FM1
FM0
FLIP Software Program
FLIP is a PC software program running under Windows(R) 9x//2000/XP, Windows NT(R) and LINUX(R) that supports all Atmel Flash microcontrollers. This free software program is available on the Atmel web site.
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In-System Programming
The ISP allows the user to program or reprogram a microcontroller's on-chip Flash memory through the serial line without removing it from the system and without the need of a pre-programmed application. This section describes how to start the UART bootloader and the higher level protocol over the serial line.
Bootloader Execution
As internal C51 code space is limited to 64K Bytes, some mechanisms are implemented to allow boot memory to be mapped in the code space for execution at addresses from F000h to FFFFh. The boot memory is enabled by setting the ENBOOT bit in AUXR1. The three ways to set this bit are detailed below. The software way to set ENBOOT consists in writing to AUXR1 from the user's software. This enables bootloader or API routines execution. The hardware condition is based on the ISP# pin. When driving this pin to low level, the chip reset sets ENBOOT and forces the reset vector to F000h instead of 0000h in order to execute the bootloader software. As shown in Figure 3, the hardware condition always allows In-System recovery when user's memory has been corrupted.
Software Boot Mapping
Hardware Condition Boot Mapping
Programmed Condition Boot Mapping
The programmed condition is based on the Bootloader Jump Bit (BLJB) in HSB. As shown in Figure 3, this bit is programmed (by hardware or software programming mode), the chip reset set ENBOOT and forces the reset vector to F000h instead of 0000h, in order to execute the bootloader software.
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Regular Boot Process Figure 3. Boot Process Algorithm
RESET
Hard Cond? ISP# = L?
Hardware Process
Prog Cond? BLJB = P?
Hard Cond Init ENBOOT = 1 PC = F000h FCON = 00h
Standard Init ENBOOT = 0 PC = 0000h FCON = F0h
Prog Cond Init ENBOOT = 1 PC = F000h FCON = F0h
Hard Init? FCON = 00h?
Software Process
User Boot? SBV < F0h?
User's Application
User's Bootloader
Atmel's Bootloader
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Physical Layer
The UART used to transmit information has the following configuration: * * * * * Character: 8-bit data Parity: none Stop: 1 bit Flow control: none Baud rate: auto baud is performed by the bootloader to compute the baud rate chosen by the host.
Frame Description
The Serial Protocol is based on the Intel Hex-type records. Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized in Table 4. Table 4. Intel Hex Type Frame
Record Mark `:' 1 byte Record length 1 byte Load Offset 2 bytes Record Type 1 byte Data or Info n byte Checksum 1 byte
* *
Record Mark: - - Record Mark is the start of frame. This field must contain ":". Record length specifies the number of Bytes of information or data which follows the Record Type field. Load Offset specifies the 16-bit starting load offset of the data Bytes, therefore this field is used only for Data Program Record. Record Type specifies the command type. This field is used to interpret the remaining information within the frame. Data/Info is a variable length field. It consists of zero or more Bytes encoded as pairs of hexadecimal digits. The meaning of data depends on the Record Type. The two's complement of the 8-bit Bytes that result from converting each pair of ASCII hexadecimal digits to one Byte of binary, and include the Record Length field to the last Byte of the Data/Info field inclusive. Therefore, the sum of all the ASCII pairs in a record after converting to binary, from the Record Length field to and the Checksum field inclusive, is zero. Record length:
*
Load Offset: -
*
Record Type: -
*
Data/Info: -
*
Checksum: -
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Protocol
Overview An initialization step must be performed after each Reset. After microcontroller reset, the bootloader waits for an auto baud sequence (see Section "Autobaud Performances", page 9). When the communication is initialized the protocol depends on the record type issued by the host. Communication Initialization The host initiates the communication by sending a "U" character to help the bootloader to compute the baud rate (auto baud). Figure 4. Initialization Host Init Communication "U" Bootloader
Performs Autobaud
If (not received "U") Else Communication Opened Time-out
"U"
Sends Back `U' Character
Autobaud Performances
The bootloader supports a wide range of baud rates. It is also adaptable to a wide range of oscillator frequencies. This is accomplished by measuring the bit-time of a single bit in a received character. This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. Table 5 shows the auto baud capabilities. Table 5. Autobaud Performances
FOSC = 12 MHz Baudrate 9600 19200 38400 57600 115200 Status OK OK OK/KO OK
1
FOSC = 16 MHz Status OK OK OK OK/KO OK/KO
1 1
FOSC = 20 MHz Status OK OK OK OK OK Error% 0.16 0.16 1.36 1.36 1.36
Error% 0.16 0.16 2.34 0.16
Error% 0.16 0.16 0.16 2.12 3.55
Note:
1. Depending on the host, error values may lead to unsupported baudrate.
Command Data Stream Protocol
All commands are sent using the same flow. Each frame sent by the host is echoed by the bootloader.
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Figure 5. Command Flow Host Sends First Character of the Frame ":" ":" Bootloader If (Not Received ":") Else Sends Echo and Start Reception
Sends Frame (Made of 2 ASCII Characters per Byte) Echo Analysis
Gets Frame, and Sends Back Echo for Each Received Byte
Programming the Flash Data
The flow described in Figure 6 shows how to program data in the Flash memory. The bootloader programs on a page of 128 bytes basis when it is possible. The host must take care that the data to program transmitted within a frame are in the same page.
Requests from Host
Command Name Program Flash Record Type 00h Load Offset Start Address Record Length nb of Data Data[0] x ... ... Data[127] x
Answers from Bootloader
The bootloader answers with: * * * "." & "CR" & "LF" when the data are programmed "X" & "CR" & "LF" if the checksum is wrong "P" & "CR" & "LF" if the Security is set
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Flow Description Figure 6. Programming Command Host
Send Write Command
Bootloader Write Command
Wait Write Command
OR Wait Checksum Error COMMAND ABORTED
Checksum Error
"X" & CR & LF
Send Checksum Error
NO_SECURITY
OR Wait Security Error COMMAND ABORTED
"P" & CR & LF
Send Security Error
Wait Programming
Wait COMMAND_OK COMMAND FINISHED
"." & CR & LF
Send COMMAND_OK
Programming Example Programming Data (write 55h at address 0010h in the Flash)
HOST BOOTLOADER : 01 0010 00 55 9A : 01 0010 00 55 9A . CR LF
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Reading the Flash Data
The flow described in Figure 7 allows the user to read data in the Flash memory. A blank check command is possible with this flow. The device splits into blocks of 16 bytes the data to transfer to the Host if the number of data to display is greater than 16 data bytes.
Requests from Host
Command Name Read Flash Blank check on Flash 04h x 05h Start Address End Address 01h Record Type Load Offset Record Length Data[0] Data[1] Data[2] Data[3] Data[4] 00h
Note:
The field "Load offset" is not used.
Answers from Bootloader
The bootloader answers to a read Flash data memory command: * * * * * * * "Address = data " & "CR" & "LF" up to 16 data by line. "X" & "CR" & "LF" if the checksum is wrong "L" & "CR" & "LF" if the Security is set "." & "CR" & "LF" when the blank check is OK "First Address wrong" "CR" & "LF" when the blank check is fail "X" & "CR" & "LF" if the checksum is wrong "P" & "CR" & "LF" if the Security is set
The bootloader answers to blank check command:
Flow Description Figure 7. Blank Check Command
Host
Send Blank Check Command
Bootloader Blank Check Command
Wait Blank Check Command
OR Wait Checksum Error COMMAND ABORTED
Checksum Error
"X" & CR & LF
Send Checksum Error
Flash Blank
OR
Wait COMMAND_OK COMMAND FINISHED
"." & CR & LF
Send COMMAND_OK
Wait Address not Erased COMMAND FINISHED
Address & CR & LF
Send First Address Not Erased
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Blank Check Example Blank Check ok
HOST BOOTLOADER : 05 0000 04 0000 7FFF 01 78 : 05 0000 04 0000 7FFF 01 78 . CR LF
Blank Check ok at address xxxx
HOST BOOTLOADER : 05 0000 04 0000 7FFF 01 78 : 05 0000 04 0000 7FFF 01 78 xxxx CR LF
Blank Check with checksum error
HOST BOOTLOADER : 05 0000 04 0000 7FFF 01 70 : 05 0000 04 0000 7FFF 01 70 X CR LF CR LF
Flow Description Figure 8. Read Command Flow Host
Send Display Command
Bootloader Display Command
Wait Display Command
OR Wait Checksum Error COMMAND ABORTED
Checksum Error
'X' & CR & LF
Send Checksum Error
RD_WR_SECURITY
OR Wait Security Error COMMAND ABORTED
'L' & CR & LF
Send Security Error
Read Data
All Data Read
Complete Frame
Wait Display Data
"Address = " "Reading value" CR & LF
Send Display Data
All Data Read
All Data Read
COMMAND FINISHED
COMMAND FINISHED
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Blank Check Example Display data from address 0000h to 0020h
HOST BOOTLOADER BOOTLOADER BOOTLOADER BOOTLOADER : 05 0000 04 0000 0020 00 D7 : 05 0000 04 0000 0020 00 D7 0000=-----data------ CR LF 0010=-----data------ CR LF 0020=data CR LF (16 data) (16 data) (1 data)
Program Configuration Information
The flow described in Figure 9 allows the user to program Configuration Information regarding the bootloader functionality. The Boot Process Configuration: BSB SBV Fuse bits (BLJB and X2 bits) (see Section "Mapping and Default Value of Hardware Security Byte", page 3) SSB
Requests from Host
Command Name Erase SBV & BSB Program SSB level1 02h Program SSB level2 Program BSB Program SBV Program bit BLJB 03h Program bit X2 0Ah 08h 03h x 03h 06h 01h 04h bit value 05h 01h 00h value Record Type Load Offset Record Length 02h Data[0] 04h Data[1] 00h 00h Data[2]
Note:
1. The field "Load Offset" is not used 2. To program the BLJB and X2 bit the "bit value" is 00h or 01h.
Answers from Bootloader
The bootloader answers with: * * * "." & "CR" & "LF" when the value is programmed "X" & "CR" & "LF" if the checksum is wrong "P" & "CR" & "LF" if the Security is set
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Figure 9. Write Command Flow Host
Send Write Command
Bootloader Write Command
Wait Write Command
OR Wait Checksum Error COMMAND ABORTED
Checksum Error
"X" & CR & LF
Send Checksum Error
NO_SECURITY
OR Wait Security Error COMMAND ABORTED
"P" & CR & LF
Send Security Error
Wait Programming
Wait COMMAND_OK COMMAND FINISHED
"." & CR & LF
Send COMMAND_OK
Program Configuration Example Programming Atmel function (write SSB to level 2)
HOST BOOTLOADER : 02 0000 03 05 01 F5 : 02 0000 03 05 01 F5. CR LF
Writing Frame (write BSB to 55h)
HOST BOOTLOADER : 03 0000 03 06 00 55 9F : 03 0000 03 06 00 55 9F . CR LF
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Read Configuration Information or Manufacturer Information Requests from Host
The flow described in Figure 10 allows the user to read the configuration or manufacturer information.
Command Name Read Manufacturer Code Read Family Code
Record Type
Load Offset
Record Length Data[0] Data[1] 00h 01h 00h 02h 03h 00h
Read Product Name Read Product Revision Read SSB Read BSB Read SBV Read HSB (Fuse bit) Read Device ID1 0Eh Read Device ID2 Read bootloader version 0Fh 0Bh 05h x 02h 07h
01h 02h 00h 00h 01h 00h
Note:
The field "Load Offset" is not used.
Answers from Bootloader
The bootloader answers with: * * * "value" & "." & "CR" & "LF" when the value is programmed "X" & "CR" & "LF" if the checksum is wrong "P" & "CR" & "LF" if the Security is set
Figure 10. Read Command Host
Send Read Command
Bootloader Read Command
Wait Read Command
OR Wait Checksum Error COMMAND ABORTED
Checksum Error
"X" & CR & LF
Send Checksum Error
RD_WR_SECURITY
OR Wait Security Error COMMAND ABORTED
"L" & CR & LF
Send Security Error
Read Value
Wait Value of Data COMMAND FINISHED
"value" & "." & CR & LF
Send Data Read
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Read Example Read function (read SBV)
HOST BOOTLOADER : 02 0000 05 07 02 F0 : 02 0000 05 07 02 F0 Value . CR LF
Atmel Read function (read bootloader version)
HOST BOOTLOADER : 02 0000 01 02 00 FB : 02 0000 01 02 00 FB Value . CR LF
Erase the Flash
The flow described in Figure 11 allows the user to erase the Flash memory. Two modes of Flash erasing are possible: * * Full Chip erase Block erase
The Full Chip erase command erases the whole Flash and sets some Configuration Bytes at their default values: * * * BSB = FFh SBV = F0h SSB = FFh (NO_SECURITY)
The full chip erase is always executed whatever the Software Security Byte value is. The Block erase command erases only a part of the Flash. Four Blocks are defined in the AT89C51SND1: * * * * Requests from Host
Command Name Erase block0 (0k to 8k) Erase block1 (8k to 16k) 02h Erase block2 (16k to 32k) Erase block2 (32k to 64k) Full chip erase 01h 07h 03h x 01h 40h 80h Record Type Load Offset Record Length Data[0] Data[1] 00h 20h
block0 (From 0000h to 1FFFh) block1 (From 2000h to 3FFFh) block2 (From 4000h to 7FFFh) block3 (From 8000h to FFFFh)
Answers from Bootloader
As the Program Configuration Information flows, the erase block command has three possible answers: * * * "." & "CR" & "LF" when the data are programmed "X" & "CR" & "LF" if the checksum is wrong "P" & "CR" & "LF" if the Security is set
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Figure 11. Erase Command Host
Send Erase Command
Bootloader Erase Command
Wait Erase Command
OR Wait Checksum Error COMMAND ABORTED
Checksum Error
"X" & CR & LF
Send Checksum Error
NO_SECURITY
OR Wait Security Error COMMAND ABORTED
"P" & CR & LF
Send Security Error
Wait Erasing
Wait COMMAND_OK COMMAND FINISHED
"." & CR & LF
Send COMMAND_OK
Example Full Chip Erase
HOST BOOTLOADER : 01 0000 03 07 F5 : 01 0000 03 07 F5 . CR LF
Erase Block1(8k to 16k)
HOST BOOTLOADER : 02 0000 03 01 20 DA : 02 0000 03 01 20 DA . CR LF
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Start the Application The command described below allows to start the application directly from the bootloader upon a specific command reception. Two options are possible: * Start the application with a reset pulse generation (using watchdog). When the device receives this command, the watchdog is enabled and the bootloader enters a waiting loop until the watchdog resets the device. Take care that if an external reset chip is used, the reset pulse in output may be wrong and in this case the reset sequence is not correctly executed. Start the application without reset A jump at the address 0000h is used to start the application without reset.
*
Requests from Host
Command Name Start application with a reset pulse generation 03h Start application with a jump at "address" x 04h Record Type Load Offset Record Length 02h 03h 01h Address Data[0] Data[1] 00h Data[2] Data[3]
Answer from Bootloader Start Application Example
No answer is returned by the device.
Start Application with reset pulse
HOST BOOTLOADER : 02 0000 03 03 00 F8 : 02 0000 03 03 00 F8
Start Application without reset at address 0000h
HOST BOOTLOADER : 04 0000 03 03 01 00 00 F5 : 04 0000 03 03 01 00 00 F5
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In-Application Programming/SelfProgramming
The IAP allows to reprogram the microcontroller's on-chip Flash memory without removing it from the system and while the embedded application is running. The user application can call some Application Programming Interface (API) routines allowing IAP. These API are executed by the bootloader. To call the corresponding API, the user must use a set of Flash_api routines which can be linked with the application. Example of Flash_api routines are available on the Atmel web site on the software application note: - C Flash Drivers for the AT89C51SND1. The flash_api routines on the package work only with the UART bootloader. The flash_api routines are listed in APPENDIX B.
API Call
Process The application selects an API by setting R1, ACC, DPTR0 and DPTR1 registers. All calls are made through a common interface "USER_CALL" at the address FFF0h. The jump at the USER_CALL must be done by LCALL instruction to be able to comeback in the application. Before jump at the USER_CALL, the bit ENBOOT in AUXR1 register must be set. Constraints The interrupts are not disabled by the bootloader. Interrupts must be disabled by user prior to jump to the USER_CALL, then re-enabled when returning. The user must take care of hardware watchdog before launching a Flash operation. For more information regarding the Flash writing time refer to the AT89C51SND1 datasheet.
API Commands
Several types of APIs are available: * * * * * Read/Program Flash Data memory Read Configuration and Manufacturer Information Program Configuration Information Erase Flash Start bootloader
Read/Program Flash Memory
All routines to access Flash data are managed directly from the application without using bootloader resources. To read the Flash memory the bootloader is not involved. For more details on these routines see the AT89C51SND1 Datasheet sections "Program/Code Memory". Two routines are available to program the Flash: - - __api_wr_code_byte __api_wr_code_page
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* The application program loads the column latches of the Flash then calls the __api_wr_code_byte or __api_wr_code_page see datasheet in section "Program/Code Memory". Parameter Settings
API_name __api_wr_code_byte R1 02h DPTR0 Address in Flash memory to write Address in XRAM of the first data to program DPTR1 ACC Value to write
*
__api_wr_code_page
09h
Address of the first Byte to program in the Flash memory
Number of Bytes to program
*
Instruction: LCALL FFF0h.
No special resources are used by the bootloader during this operation
Note:
Read Configuration and Manufacturer Information
*
Parameter Settings
API_name __api_rd_HSB __api_rd_BSB __api_rd_SBV __api_rd_SSB __api_rd_manufacturer __api_rd_device_id1 __api_rd_device_id2 __api_rd_device_id3 __api_rd_bootloader_v ersion R1 0Bh 07h 07h 07h 00h 00h 00h 00h 0Fh DPTR0 0000h 0001h 0002h 0000h 0000h 0001h 0002h 0003h 0000h DPTR1 x x x x x x x x x ACC return HSB return BSB return SBV return SSB return manufacturer id return id1 return id2 return id3 return version value
* *
Instruction: LCALL FFF0h. At the complete API execution by the bootloader, the value to read is in the api_value variable.
No special resources are used by the bootloader during this operation.
Note:
Program Configuration Information
*
Parameter Settings
API_name __api_set_X2 __api_clr_X2 __api_set_BLJB __api_clr_BLJB __api_wr_BSB __api_wr_SBV __api_wr_SSB_LEVEL0 R1 0Ah 0Ah 0Ah 0Ah 06h 06h 05h DPTR0 0008h 0008h 0004h 0004h 0000h 0001h FFh DPTR1 x x x x x x x ACC 00h 01h 00h 01h value to write value to write x
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*
Parameter Settings (Continued)
API_name __api_wr_SSB_LEVEL1 R1 05h 05h DPTR0 FEh FCh DPTR1 x x ACC x x
__api_wr_SSB_LEVEL2
*
Instruction: LCALL FFF0h.
1. Refer to the AT89C51SND1 datasheet for information on write operation timing. 2. No special resources are used by the bootloader during these operations.
Note:
Erase Flash
The AT89C51SND1 Flash memory is divided in four blocks: Block 0: from address 0000h to 1FFFh (64 pages) Block 1: from address 2000h to 3FFFh (64 pages) Block 2: from address 4000h to 7FFFh (128 pages) Block 3: from address 8000h to FFFFh (256 pages) * Parameter Settings
API_name __api_erase_block0 __api_erase_block1 01h __api_erase_block2 __api_erase_block3 4000h 8000h x x x x R1 DPTR0 0000h 2000h DPTR1 x x ACC x x
*
Instruction: LCALL FFF0h.
1. Refer to the AT89C51SND1 datasheet for information on write operation timing and multiply this timing by the number of pages. 2. No special resources are used by the bootloader during these operations
Note:
Start Bootloader
This routine allows to start at the beginning of the bootloader as after a reset. After calling this routine the regular boot process is performed and the communication must be opened before any action. * * * No special parameter setting Set bit ENBOOT in AUXR1 register instruction: LJUMP or LCALL at address F000h
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Appendix A
Table 6. Summary of Frames From Host
Command Program Nb Data Byte in Flash. Erase block0 (0000h-1FFFh) Erase block1 (2000h-3FFFh) 02h Erase block2 (4000h-7FFFh) Erase block3 (8000h-FFFFh) Start application with a reset pulse generation Start application with a jump at "address" Erase SBV & BSB Program SSB level 1 Program SSB level 2 Program BSB 03h Program SBV Full Chip Erase Program bit BLJB 03h Program bit X2 Read Flash 04h Blank Check Read Manufacturer Code Read Family Code 00h Read Product Name Read Product Revision Read SSB Read BSB Read SBV Read Hardware Byte Read Device Boot ID1 0Eh Read Device Boot ID2 Read bootloader Version 0Fh 01h 00h - - - - - - 0Bh 05h 02h x 07h 02h 03h 00h 01h 02h 00h 00h - - - - - - - - - - - - - - - - - - - - - 00h 01h - - - - 05h x Start Address End Address 01h - - x 01h x x x 0Ah 08h bit value - - 00h 07h 03h 02h 02h 04h x 03h x x x 05h x x 06h 01h 04h value - bit value - - - - - - 01h 00h - value - - - - 04h 01h 00h 00h - - address - - - - - x 01h 40h 80h 00h - - - - - - - - - Record Type 00h Record Length nb of data (up to 128) Offset start address Data[0] x Data[1] x 00h 20h Data[2] x - - Data[3] x - - Data[4] x - -
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Appendix B
Table 7. API Summary
Function_Name __api_rd_code_byte __api_wr_code_byte Bootloader Execution no yes 02h Address in Flash memory to write Address of first Byte to program in Flash memory 0000h 2000h 4000h 8000h 0000h 0008h 0008h 0004h 0004h 0001h 0000h 0002h 0001h 0001h 0000h 00FFh 00FEh 00FCh 0000h 0001h 0002h 0003h 0000h - - Address in XRAM of the first data to program x x x x x x x x x x x x x x x x x x x x x x x - Value to write R1 DPTR0 DPTR1 ACC
__api_wr_code_page
yes
09h
Number of Byte to program
__api_erase_block0 __api_erase_block1 __api_erase_block2 __api_erase_block3 __api_rd_HSB __api_set_X2 __api_clr_X2 __api_set_BLJB __api_clr_BLJB __api_rd_BSB __api_wr_BSB __api_rd_SBV __api_wr_SBV __api_erase_SBV __api_rd_SSB __api_wr_SSB_level0 __api_wr_SSB_level1 __api_wr_SSB_level2 __api_rd_manufacturer __api_rd_device_id1 __api_rd_device_id2 __api_rd_device_id3 __api_rd_bootloader_version __api_start_bootloader
yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes no
01h 01h 01h 01h 0Bh 0Ah 0Ah 0Ah 0Ah 07h 06h 07h 06h 06h 07h 05h 05h 05h 00h 00h 00h 00h 0Fh -
x x x x return value 00h 01h 00h 01h return value value return value value FCh return value x x x return value return value return value return value return value -
24
AT89C51SND1 UART Bootloader
4241B-MP3-07/04
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4241B-MP3-07/04 /xM

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